High data reliability, reduced chip size, reduced power consumption and efficient power usage are features that are demanded from semiconductor memory. In order to enhance current driving capability while suppressing chips size increase, a buffer circuit in a conventional semiconductor device includes a plurality of transistors coupled in parallel to each other.
For example, an inverter buffer circuit includes a plurality of p-channel field-effect transistors and a plurality of n-channel field-effect transistors. The plurality of p-channel field-effect transistors are coupled in parallel to each other between a power supply voltage line for a power supply voltage (e.g., VPERI, VDD) and an output node, and the plurality of n-channel field-effect transistors are coupled in parallel to each other between another power supply voltage line for reference voltage (e.g., VSS, Ground) that is different from the power supply voltage (e.g., the reference voltage is lower than the power supply voltage), and the output node. Gates of the p-channel and n-channel field-effect transistors are coupled in common to an input node. As the plurality of p-channel field-effect transistors are coupled in parallel to each other, the adjacent two transistors of the plurality of p-channel field-effect transistors are formed to share a common source region (P-type) with each other. Similarly, the adjacent two transistors of the plurality of n-channel field-effect transistors are formed to share a common source region (N-type) with each other. Sharing a common source region causes increase in current density at the common source region that results in large voltage drop (IR drop) of a source potential. To avoid such large voltage drop, recent conventional semiconductor devices tend to include a plurality of transistors coupled in parallel to each other has been fabricated with an individual and separated source region. Thus, the source regions of the adjacent transistors have been separated from each other.
FIG. 1A is a circuit diagram of a conventional inverter buffer including two p-channel field-effect transistors and two n-channel field-effect transistors. FIG. 1B is a layout diagram of the conventional inverter buffer. FIG. 1C is a schematic diagram of the conventional inverter buffer and includes a cross sectional view along a line A-A′ in FIG. 1B of the adjacent p-channel filed effect transistors and a cross sectional view along a line B-B′ in FIG. 1B of the adjacent n-channel filed effect transistors. As shown, the source regions of the two p-channel filed effect transistors are separated from each other by a shallow trench isolation (STI) to avoid large IR drop. Similarly, the source regions of the two n-channel filed effect transistors are separated from each other by another STI. Each box over the STI is a dummy gate that is formed (or patterned) simultaneously with gates of the p-channel filed effect transistors and N-channel filed effect transistors in order to achieve uniformity in forming the gates of the transistors. However, such separation causes increase in chip size and complication of layout patterns, if combined with other layout restraints.